Fill level indicator for self-timed fifo

ABSTRACT

A FIFO uses a fill indicator circuit to indicate a fill status and provide control signals to a data source and data sink to cease operation. A serial string of FIFO cells propagates data from input to output by sending request and acknowledge signals between adjacent cells. The request signal initiates data transfer to the next logical cell and the acknowledge signal indicates completion of the transfer. The fill indicator has one cell for each FIFO cell for monitoring the request and acknowledge signals looking for predetermined state sequences to indicate whether each FIFO cell is full or empty.

BACKGROUND OF THE INVENTION

The present invention relates in general to first-in-first-out (FIFO)circuits and, more particularly, to a FIFO operating with a fill levelindicator.

Many data processing and communication applications, for examplecomputer networks, require data communication between devices operatingasynchronously. One problem with asynchronous communication is that datatransmission between data source and data sink must be carefullycontrolled to prevent loss of data. If the data source transmitsinformation faster than the data sink can accept, information may belost. Alternately, if the data sink accepts information faster than thedata source can provide, the data sink may capture the same data twice.Hence, there must be control over asynchronously transmitted data.

One solution found in the prior art involves handshaking between thedata source and data sink. The data source does not send data until thedata sink is ready. Likewise, the data sink does not read until the datasource indicates that valid data is present. The handshaking proceduretends to slow the communication process and result in inefficientoperation because the higher operating speed of the data source or datasink cannot be fully utilized.

Another solution is to insert an asynchronous buffer, e.g. FIFO, betweenthe data source and data sink. The data source may dump data into thebuffer at its nominal operating speed. The data sink reads from thebuffer at will. The inherent limitation in the buffer approach is itsfinite length. If the data source is faster than the data sink for someperiod of time, then the buffer may overflow causing loss of data. Ifthe data sink is faster than the data source, the buffer may becomeempty and the data sink may read invalid data. Hence, the data sourceand sink must have feedback from the buffer to help regulate when toenable and disable the flow of data.

Unfortunately, it is difficult to obtain reliable indication of fillstatus from an asynchronous buffer. If the buffer is implemented as adual-port RAM with pointers to the first and last location, then asubtractor circuit could compute the difference between the pointersindicating full status of the buffer. However since either pointer canchange asynchronously, there is some chance that the data source or datasink will attempt to read the value while it is changing resulting in asignificant error.

Hence, a need exists to detect the fill status of an interface bufferbetween the data source and data sink in a manner that is not subject toserious errors common in asynchronous systems.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram illustrating a FIFO with fill indicator;

FIG. 2 is a block diagram illustrating adjacent cells of the FIFO ofFIG. 1;

FIG. 3 is a schematic diagram illustrating one FIFO cell of FIG. 2;

FIG. 4 is a schematic diagram illustrating one cell of the fillindicator of FIG. 2; and

FIG. 5 is a state diagram illustrating the operation of the fillindicator cell of FIG. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A communication circuit 10 is shown in FIG. 1 suitable for manufacturingas an integrated circuit using conventional integrated circuitprocesses. A data source 12 operating with CLOCK1 transmits data to FIFO14 for storage. The data signal may comprise any width of logical word.A control signal ENQUEUE indicates to FIFO 14 that data is valid forstorage. FIFO 14 shifts data received at its input in afirst-in-first-out fashion along a string of serially coupled datastorage cells to an output. FIFO 14 is self-timed where receipt of datain one cell triggers transfer to the next cell if space is available.Data sink 16 operating with CLOCK2 receives data from FIFO 14 forfurther processing. CLOCK1 is asynchronous with respect to CLOCK2. Acontrol signal DEQUEUE indicates to FIFO 14 that data has been readallowing the remaining data in the queue to shift toward the output.With different clock sources, data source 12 and data sink 16 mayoperate asynchronously. Hence, FIFO 14 functions as intermediate storageuntil data sink 16 accepts the data.

As part of the present invention, fill indicator 20 receives controlsignals from FIFO 14 and provides status indicators STOP₋₋ SENDING andSTOP₋₋ RECEIVING to data source 12 and data sink 16, respectively. TheSTOP₋₋ SENDING signal is asserted when FIFO 14 has say two or threecells available for data. The STOP₋₋ RECEIVING signal is asserted whenFIFO 14 has say two or three cells with data remaining. The early STOP₋₋SENDING and STOP₋₋ RECEIVING indicators allow data source 12 and datasink 16 plenty of time to disable operation before data runs out oroverflows.

Further detail of the interconnection between FIFO 14 and fill indicator20 is shown in FIG. 2 with FIFO 14 including FIFO cell 22 receiving adata word from data source 12. The data output of FIFO cell 22 iscoupled to the data input of FIFO cell 24. The last FIFO cell 26 has adata output coupled to the input of data sink 16. FIFO cells 22-26provide control signals REQ (request) and ACK (acknowledge) to fillindicator cells 28, 30 and 32, respectively. Fill indicator cells 28-32pass FFLG (full flag) signals as shown. The FLEV (fill level) outputsfrom fill indicator cells 28-32 provide the desired fill status.

Note the convention in naming signals running between iterative cells.For example, the signal running between fill indicator cells such ascells 28 and 30 is generically referred to as FFLG. The output from cell30 producing FFLG is labeled FFLGO, and the input that FFLG goes to islabeled FFLGI. REQ and ACK signals are labeled similarly. In general, asignal is considered to be asserted at logic one, and negated at logiczero.

FIFO cell 22 is illustrated in FIG. 3 as representative of the otherFIFO cells. The width of the data signal shown is only one bit, thoughit could be any width. The circuit comprising elements 48-54 would berepeated for each bit in the data word.

Assume FIFO cell 22 begins in an empty state. The FULL signal at theoutput of RS latch 36 comprising NOR gates 38 and 40 is logic zero.Inverters 42 and 46 provide delay to avoid timing problems in theself-timed logic. To move data into FIFO cell 22, the ENQUEUE isasserted low and comes in as REQI. Since both inputs to NOR gate 44 arelow its output goes to logic one thereby enabling transistor 48. Thedata signal passes through transistor 48 to inverters 50 and 52. Thelogic one output from NOR gate 44 also asserts the ACKO pulse as logicone to data source 12 acknowledging the receipt of the data. The logicone from NOR gate 44 also sets the output of RS latch 36 such that theFULL signal becomes logic one and the FULL signal goes to logic zero.The logic one FULL signal enables transistor 54 to latch the data acrossinverters 50 and 52. The logic one FULL signal also causes the output ofNOR gate 44 to return to logic zero, whereby ACKO returns to logic zeroand turns off transistor 48. Upon receiving the ACKO signal, data source12 returns the REQI signal to logic one.

The FULL signal becomes the REQO signal to FIFO cell 24 in preparationfor the next move of the data word. If space is available in FIFO cell24 and the transfer is successful, its ACKO pulse returns to FIFO cell22 as the ACKI pulse to reset RS latch 36. The FULL signal returns tologic zero making FIFO cell 22 available for more input data. Theremaining FIFO cells are connected in a similar manner to accomplish thefirst-in-first-out operation. The FULL signal from FIFO cell 26 goes todata sink 16 to indicate data is ready to be read from FIFO 14. TheDEQUEUE signal from data sink 16 becomes the ACKI signal for FIFO cell26. Thus, data input to FIFO cell 22 ripples to the end of FIFO 14 whereit is made available to data sink 16.

A key feature of the present invention is provided by fill indicator 20to monitor the state changes of each FIFO cell and provide FLEV statussignals indicating the fill status of FIFO 14. Turning to FIG. 4, fillindicator cell 30 is shown as representative of the other cells. TheFFLGI signal from FFLGO of the previous fill indicator cell, e.g. cell32, is applied to one input of NAND gate 60. The REQI signal from REQ ofFIFO cell 22 is applied to a second input of NAND gate 60. The REQIsignal is also inverted by inverter 62 and applied to inputs of NANDgates 64 and 66. The ACKI pulse is applied to one input of NAND gate 68and through inverter 70 to inputs of NAND signal from initializationlogic (not shown). NAND gate 74 receives its inputs from NAND gates 66and 72. The output of NAND gate 74 noted as STATE0 is coupled to inputsof NAND gates 60, 76 and 72. NAND gate 78 receives its inputs from NANDgates 60, 64, 68 and 76. The output of NAND gate 78 noted as STATE1 iscoupled to inputs of NAND gates 64, 68 and 76. The output of NAND gate76 also provides the FFLGO signal following inversion by inverter 80.

The operation of fill indicator cell 30 may best be understood incombination with state diagram 82 shown in FIG. 5. State diagram 82 is afour-state asynchronous state machine which may be implemented as shownin FIG. 4. It should be readily apparent that other logic configurationsalthough not specifically shown may achieve the same result and areconsidered within the scope of this invention. State diagram 82 isasynchronous in that it changes state upon the condition between thestates becoming true, without reference to any clock. In FIG. 5 and thefollowing, a dot ,,e,, refers to the logical AND operator, REQI refersto the inverse of signal REQI, ACKI refers to the inverse of signalACKI, and FFLGI refers to the inverse of signal FFLGI. The states instate diagram 82 are labeled with the state name, followed by a slash"/", followed by the output of the state. An output of FLEV means thatthe FLEV signal is at logic one and an output of FLEV indicates that theFLEV signal is at logic zero. The same notation applies for outputFFLGO.

State 84 is the empty state indicating no data in the corresponding FIFOcell. In the empty state both outputs FLEV and FFLGO are at logic zero,and STATE0 and STATE1 are at logic zero. When REQI is at logic one andACKI is at logic zero, satisfying the transition condition REQI  ACKI,state diagram 82 switches to propagating state 86. Propagating state 86corresponds to STATE0 at logic one and STATE1 at logic zero.

For example, consider the operation of fill indicator cell 30 in FIG. 4when it is in the empty state with REQI at logic zero, indicating norequest, and ACKI at logic zero, indicating that the next data cell isnot acknowledging data transfer, i.e. any previous transfer of data outof FIFO cell 24 is complete. NAND gate 60 receives logic zero fromSTATE0 and provides a logic one to NAND gate 78. NAND gate 64 receives alogic zero from STATE1 and provides another logic one to NAND gate 78.The inputs to NAND gate 68 are logic zeroes from STATE1 and ACKIproducing a logic one output. Likewise, the output of NAND gate 76 islogic one with logic zeroes from STATE0 and STATE1. NAND gate 66receives a logic zero from REQI and provides a logic one to NAND gate66. NAND gate 72 receives a logic zero from STATE0 and provides anotherlogic one to NAND gate 66. Both NAND gates 78 and 66 have all inputs atlogic one and therefore produce logic zero outputs, so state diagram 82remains steady state in empty state 84.

Now assume ACKI remains at logic zero and REQI changes to logic one,which satisfies the transition condition REQI  ACKI. This occurs whenthe FIFO cell is receiving a request to write data and any previoustransfer of data out of this FIFO cell has been completed. NAND gate 66checks the combination of REQI and ACKI true and provides a logic zerooutput to NAND gate 74. The output of NAND gate 74 goes to logic one andchanges STATE0 accordingly. Despite these changes, the other NAND gates60-72 continue to produce logic one outputs since each still has atleast one input at logic zero. In particular, NAND gate 60 gained alogic zero input from REQI before its STATE0 input changed to logic one,and NAND gates 64 and 76 each have a logic zero input from STATE1. Hencestate diagram 82 has moved to propagating state 86 with STATE0 at logicone and STATE1 at logic zero. FIFO cell 24 now contains data, althoughthe fill level output signal FLEV is still low because the data may bejust rippling through this cell.

Continuing with FIG. 5, after a short time REQI will go to logic zero,indicating that the transfer of data into FIFO cell 24 is complete. Oneof two cases will occur. If the next FIFO cell is empty, FFLGI will beat logic zero, and ACKI will go to logic one, indicating that the nextFIFO cell is accepting the data from FIFO cell 24. This case satisfiesthe condition ACKI  FFLGI, causing state diagram 82 to switch back toempty state 84. Data was merely passing through the corresponding FIFOcell. Note that both empty state 84 and propagating state 86 provide alogic zero FLEV status indicating that the corresponding FIFO cell doesnot contain data, so the propagation of data through the FIFO cell didnot produce any undesired pulse in the FLEV output.

Returning to propagating state 86, a second case occurs if the next cellwas already occupied with data. The next fill indicator cell provides alogic one on FFLGI, and no ACKI arrives because the next FIFO is alreadyfull and cannot acknowledge more data. Hence when REQI goes to logiczero, the transition condition REQI  ACKI  FFLGI is satisfied. Statediagram 82 switches to full state 88 corresponding to STATE0 and STATE 1as logic one. The full flag output FFLGO and the fill level output FLEVare logic one. Once data moves out of the next FIFO cell with ACKIasserted at logic one, state diagram 82 jumps to clearing state 90. Theclearing state 90 corresponds to STATE0 at logic zero and STATE 1 aslogic one. FLEV is logic one. If data comes right back into FIFO cell 24again, i.e. REQI and ACKI at logic one, then state diagram 82 returns tofull state 88. Hence if FIFO cells 28-32 are occupied with data, and oneword of data is read from the FIFO causing all other words to move overto the next cell, fill indicator cell 30 moves briefly to clearing state90 and then returns to full state 88 as data moves in from FIFO cell 22.Since both clearing state 90 and full state 88 produce logic one on theFLEV output, there is no undesired pulse in the FLEV output. In clearingstate 90, if no data is waiting in FIFO cell 22 to move into FIFO cell24, then the transition condition REQI  ACKI is satisfied, and statediagram 82 moves to empty state 84.

Once the FLEV status signal is set at logic one or logic zerocorresponding to whether or not data exists in the FIFO cells, theSTOP₋₋ SENDING and STOP₋₋ RECEIVING control signals shown in FIG. 1,which may be selected as any one of the FLEV status signals to disabledata source 12 and data sink 16, respectively.

While specific embodiments of the present invention have been shown anddescribed, further modifications and improvements will occur to thoseskilled in the art. It is understood that the invention is not limitedto the particular forms shown and it is intended for the appended claimsto cover all modifications which do not depart from the spirit and scopeof this invention.

What is claimed is:
 1. A circuit, comprising:first means for shiftingdata received at an input along a string of serially coupled datastorage cells to an output where each of said data storage cellsprovides a request control signal indicating a request for data transferto a first adjacent cell and an acknowledge control signal acknowledgingdata transfer from a second adjacent cell; and second means coupled forreceiving said request and acknowledge control signals and determiningfill status of said data storage cells in a predetermined manner andproviding a fill level signal accordingly, said second means includes astring of serially coupled fill indicator cells where a first fillindicator cell receives a full flag input signal from a second fillindicator cell adjacent to said first fill indicator Cell, said firstfill indicator cell including,(a) a first NAND gate having first, secondand third inputs and an output, said first input receiving a first statesignal of said first fill indicator cell, said second input receivingsaid full flag input signal, said third input receiving said requestcontrol signal, (b) a second NAND gate having first and second inputsand an output, said first input receiving a second state signal of saidfirst fill indicator cell, said second input receiving an invertedrequest control signal, (c) a third NAND gate having first and secondinputs and an output, said first input receiving said second statesignal of said first fill indicator cell, said second input receivingsaid acknowledge control signal, (d) a fourth NAND gate having first andsecond inputs and an output, said first input receiving said first statesignal of said first fill indicator cell, said second input receivingsaid second state signal of said first fill indicator cell, said outputproviding a second full flag output signal, and (e) a fifth NAND gatehaving first, second, third and fourth inputs and an output, said firstinput being coupled to said output of said first NAND gate, said secondinput being coupled to said output of said second NAND gate, said thirdinput being coupled to said output of said third NAND gate, said fourthinput being coupled to said output of said fourth NAND gate, said outputproviding said fill level signal and said second state signal of saidfirst fill indicator cell.
 2. The circuit of claim 1 wherein said firstfill indicator cell further includes:a sixth NAND gate having first andsecond inputs and an output, said first input receiving said invertedrequest control signal of said first fill indicator cell, said secondinput receiving an inverted acknowledge control signal; a seventh NANDgate having first, second and third inputs and an output, said firstinput receiving said first state signal of said first fill indicatorcell, said second input receiving said inverted acknowledge controlsignal, said third input receiving a reset control signal; and an eighthNAND gate having first and second inputs and an output, said first inputbeing coupled to said output of said sixth NAND gate, said second inputbeing coupled to said output of said seventh NAND gate, said outputproviding said first state of said first fill indicator cell.
 3. Amethod of determining fill status of a data storage cell, comprising thesteps of:establishing an empty state indicating that the data storagecell is available for data input; monitoring status of request andacknowledge control signals where said request control signal indicatesa request for data transfer to a first adjacent data storage cell andsaid acknowledge control signal acknowledges data transfer to a secondadjacent data storage cell; shifting from said empty state to apropagation state when said request control signal and an invertedacknowledge control signal are asserted; and shifting from saidpropagation state to a full state when an inverted request controlsignal and said inverted acknowledge control signal and a full flagsignal are asserted, where said full state provides the fill status anda full flag signal to the adjacent cell.
 4. The method of claim 3further comprising the step of shifting from said full state to aclearing state when said acknowledge control signal is asserted, wherethe clearing state provides the fill status.
 5. The method of claim 4further comprising the step of shifting from said clearing state to saidempty state when said inverted request control signal and said invertedacknowledge control are asserted.
 6. The method of claim 5 furthercomprising the step of shifting from said clearing state to said fullstate when said request control signal and said inverted acknowledgecontrol are asserted.
 7. The method of claim 6 further comprising thestep of shifting from said propagation state to said empty state whensaid acknowledge control signal and an inverted full flag signal areasserted.
 8. A circuit, comprising:first means for shifting datareceived at an input along a string of serially coupled data storagecells to an output where each of said data storage cells provides arequest control signal indicating a request for data transfer to a firstadjacent cell and an acknowledge control signal acknowledging datatransfer from a second adjacent cell; and a string of serially coupledfill indicator cells where a first fill indicator cell receives a fullflag signal from a second fill indicator cell adjacent to said firstfill indicator cell, said first fill indicator cell including,(a) afirst NAND gate having first, second and third inputs and an output,said first input receiving a first state signal of said first fillindicator cell, said second input receiving said full flag input signal,said third input receiving said request control signal, (b) a secondNAND gate having first and second inputs and an output, said first inputreceiving a second state signal of said first fill indicator cell, saidsecond input receiving an inverted request control signal, (c) a thirdNAND gate having first and second inputs and an output, said first inputreceiving a second state signal of said first fill indicator cell, saidsecond input receiving said acknowledge control signal, (d) a fourthNAND gate having first and second inputs and an output, said first inputreceiving said first state signal of said first fill indicator cell,said second input receiving said second state signal of said first fillindicator cell, said output providing a second full flag output signal,and (e) a fifth NAND gate having first, second, third and fourth inputsand an output, said first input being coupled to said output of saidfirst NAND gate, said second input being coupled to said output of saidsecond NAND gate, said third input being coupled to said output of saidthird NAND gate, said fourth input being coupled to said output of saidfourth NAND gate, said output providing said fill level signal and saidsecond state signal of said first fill indicator cell.
 9. The circuit ofclaim 8 wherein said first fill indicator cell further includes:a sixthNAND gate having first and second inputs and an output, said first inputreceiving said inverted request control signal of said first fillindicator cell, said second input receiving an inverted acknowledgecontrol signal; a seventh NAND gate having first, second and thirdinputs and an output, said first input receiving said first state signalof said first fill indicator cell, said second input receiving saidinverted acknowledge control signal, said third input receiving a resetcontrol signal; and an eighth NAND gate having first and second inputsand an output, said first input being coupled to said output of saidsixth NAND gate, said second input being coupled to said output of saidseventh NAND gate, said output providing said first state of said firstfill indicator cell.